Low power address bus encoding using loop prediction

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Low power address bus encoding using loop prediction

This paper proposes a loop prediction encoding method for decreasing power consumption on instruction memory address bus. The loop prediction encoding is based on detecting and predicting loop programs. The experiment results show that our method can decrease switching activity up to 81.5% on average, with small overheads on performance and area.

متن کامل

Low-Power Data Address Bus Encoding Method

Reducing power consumption of computer systems has gained much research attention recently. In a typical system, the memory bus power constitute will over 50% of all system power; and this power is required due to bus signal transitions (0 1 or 1 0). Reducing the number of memory bus transitions is hence an effective way to reduce system power. While many techniques deal with reducing bus power...

متن کامل

Power-optimal Encoding for DRAM Address Bus

This paper presents Pyramid code, an optimal code for transmitting sequential addresses over a DRAM bus. Constructed by finding an Eulerian cycle on a complete graph, this code is optimal for conventional DRAM in the sense that it minimizes the switching activity on the time-multiplexed address bus from CPU to DRAM. Experimental results on a large number of testbenches with different characteri...

متن کامل

Bus-Switch Encoding for Power Optimization of Address Bus

This paper presents a novel encoding technique to minimize the switch activities on the highly capacitive memory address bus so as to reduce power dissipation of bus. This technique is based on the temporal locality and spatial locality of instruction address. The experimental results based on an instruction set simulator and SPEC2000 benchmarks show that the presented encoding technique can re...

متن کامل

Power-optimal encoding for a DRAM address bus

This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). For external switching activity in a sequential access pattern, we present a power-opt...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEICE Electronics Express

سال: 2014

ISSN: 1349-2543

DOI: 10.1587/elex.11.20140379